Sources
- Lecture Slides
Practice Exercise
- Draw a logic diagram of a fully-buffered CPU Module based on the 8086 microprocessor in minimum mode
- Draw a logic diagram of a fully-buffered CPU Module based on the 8086 microprocessor in maximum mode
Draw a clock diagram:
- clock generator
- 8086 - connected to the octal buffer
- 3 74LS73 - output of buffer is address bus
- 2 74LS245 - output of transceiver is the data bus
- 2 74LS244
Digital Computer
Block Diagram of the 4 Main Components of the Computer.
When the four components are combined into 1 integrated circuit, it is known as a Microcontroller—a complete computer system
- Central Processing Unit - performs all the processing like arithmetic and logic operations, decision making, and control functions1
- Control unit
- Processing Unit/Datapath
- Memory Unit - store instructions and data to be processed by the program
- Cache Memory - fast but small, volatile2
- Instruction Cache
- Data Cache
- Main Memory - slower but has a larger capacity than cache, volatile
- ROM - read only memory
- RWM (aka RAM) - read and write memory
- Secondary Memory - much slower than main memory, but very large capacity, non-volatile
- Hard Disk
- USB Flash Disk
- Archival Memory - very slow but very large capacity, used for backup and recovery
- CD/DVD
- Cache Memory - fast but small, volatile2
- IO Unit - for interconnecting the environment with the computer, so allows us to interact with the computer
- input port
- Peripheral devices3
- Switches
- Keyboard
- ADC/Data Acquisition System - allows computer to receive data coming from sensors
- Pointing Devices (e.g., mouse)
- Peripheral devices3
- output port
- Peripheral Devices
- LEDs/indicator lamps
- 7 segment/LC Display
- DAC
- Video Display Unit
- Printer/Plotter
- Peripheral Devices
- input port
- System bus - facilitates communication between the other three components
- Standards that govern the system bus
- PLB
- AXI
- ISA
- PCI
- Standards that govern the system bus
Microprocessor
- It has 3 groups of signals
- Address bus (M bits) - carries information to identify the component where data transfer with microprocessor will occur
- the number of addressable/accessible locations. In other words, the number of devices that can be accessed by the microprocessor
- Data bus (N bits) - the path where data flows to get to the desired address
- Control bus - governs the data transfer direction (e.g., processor to output, input to processor, etc.)
- READ - memory → microprocessor
- WRITE - microprocessor → memory
- IO/M - InputOutput/Memory
- 0 = microprocessor → IO
- 1 = microprocessor → memory
- RESET - brings the processor to a known starting state
- INT
- INTA
- Address bus (M bits) - carries information to identify the component where data transfer with microprocessor will occur
- The 3 signals connects it to the system bus
- Bus Cycles - 4 possible that happens in the CPU module
- READ - data is transferred from memory/io to microprocessor (MP)
- MP outputs address to address bus
- MP activates control for read operation
- Memory output data to data bus
- MP gets data from data bus
- WRITE- data is transferred from MP to memory/io
- MP outputs address to address bus
- MP outputs data to the data bus
- MP activates control for write operation
- Memory gets data from data bus and stores it to the addressed location
- READ - data is transferred from memory/io to microprocessor (MP)
Computer as a Controller Example
Composed of and are connected:
- Microcontroller
- Set Point
- Temp
- Time
- Control Element
- Temp Sensor
- Heating Element
- Control Element
Creating this system involves interfacing
8086
- Address where first program is located - FFFF0
Recommended configuration based on the datasheet typical minimum config:
- Microprocessor 8086
- 8284 Clock generator
- 2-3 Latches - separate the address signal from the data signal (demultiplexing) and maintain a constant address signal on the system bus.
- Transceiver (transmitter transceiver) - allows data to pass in both direction. like latches but for data signals instead of address signals
- Ram
- PROM - contains the program that contains the control code
- Peripheral - interconnection point between keypad and ADC
Pins that provide the 3 signals for 8284 and 8086 connection:4
- ready
- reset
- clock
- S2,S1,S0
- M/IO
- WR
- RD
- BHE - enables data to the most significant half. only useful when data is 16 bit wide
- multiplexed (or somewhat combined) address data bus
octal latch 74LS73, look at the logic/function table to understand how it operates
octal bus transceiver SN74LS245 and SN74LS373
- look at the pin outs
- DIR determines whether it will go a to b or b to a
- look at the function table for more info
Timing Diagram - shows the operation
- insert the clock
if you want to extend the machine/clock cycle - this is useful for old devices where delay is used for io devices to catch up
- ALE is a signal that indicates whether the signal is at state T1 or not
- This is crucial because the multiplex address data bus contains address information during T1
- Is connected to clock of latch
- the address/data address is the signal to be stored in the octal buffer
- left side of clock is the read cycle, while right is write cycle
- DT/R is the data transmit receive
- active low R means that transceiver is set to receive, or data transfer is from side b to a
- connected to DIR of transceiver
- DEN - data enable for enabling the transceiver
- is connected to the gate enabled of the transceiver
Minimum Mode Vs Maximum Mode
- Minimum mode - only 1 processor
- Maximum mode - assumes multiple processors